1. Field of the Invention
The present invention relates to a semiconductor memory including a serial data output control circuit, such as an image memory.
2. Description of the Related Art
In recent years, strong demand for achieving a high-speed operation of a semiconductor memory has arisen in various fields, and the demand for a semiconductor memory capable of serial access has increased. Such a conventional semiconductor memory, e.g., an image memory, includes a random access memory section (hereinafter called a RAM section) capable of performing random access, and a serial access memory section (hereinafter called a SAM section) capable of performing serial access. Data are transferred between the RAM and SAM sections through read and write latch sections, and asynchronous access of the RAM and SAM sections is performed.
The RAM section has the same arrangement as that of a conventional dynamic or static memory. An access method of the RAM section is substantially the same as in the dynamic or static memory. The SAM sections are classified into two types. One is a section for serially transferring data in practice using a shift register. The other one is a section for realizing serial access by sequentially accessing the read and write latch sections. In this case, the former section using a shift register will be described below.
FIG. 1 shows an arrangement of an image memory using shift registers in serial input and output section, respectively. Reference symbol SRi denotes an input shift register; WL, a write latch section; MC, a memory cell array; RL, a read latch section; SRo, an output shift register; RAMC, a RAM control circuit; AD, an address decoder; SAMC, a SAM control circuit; CE, a control signal for the RAM section; WE, a write/read control signal for the RAM section; Din, write data to be serially input; Dout, readout data to be serially output; SC, a control clock input for the SAM section; and WS, a signal for controlling a data transfer operation from the input shift register SRi to the write latch section WL.
FIG. 2 shows an arrangement of the serial input section constituted by, e.g., four shift registers SR1 to SR4. FIG. 3 is a timing chart of the serial input section shown in FIG. 2. The serial input data Din are sequentially received by the shift registers SR1 to SR4 in response to the clock input SC, and are respectively written in write latches WL1 to WL4 in response to the signal WS every 4-bit input. These data are written into a memory cell array in response to a signal WRT prior to writing of new data in the write latches WL1 to WL4 in response to a next output signal WS. The signal WRT is formed from the control signals CE and WE for the RAM section. The signal WRT allows a write operation to the memory cell array while being asynchronous with the clock input SC and the signal WS.
FIG. 4 shows an arrangement of the serial output section constituted by, e.g., four shift registers SRI to SR4. FIG. 5 is a timing chart of the serial output section shown in FIG. 4. Data in the memory cell array are read out and latched by read latches RL1 to RL4 in response to a signal RLT formed by the control signals CE and WE for the RAM section. Then, outputs from the read latches RL1 to RL4 are respectively selected by selectors Y1 to Y4 in response to the signal RS, and the selected outputs are sequentially received by the shift registers SR1 to SR4 at a leading edge of the clock input SC. The received outputs are sequentially output from the shift register SR4 as serial output data Dout. In the same manner as in the serial input operation, the signal RLT can read the contents of the memory cells and stores the readout data in the read latches RL1 to RL4 while being asynchronous with the clock input SC before the signal RS is output.
In the image memory shown in FIG. 1, the serial input and output sections may be preferably arranged adjacent to the memory cell array. In this case, a relatively long wiring is required to connect the serial input and output sections to the external clock input SC and the serial input data Din, and the external serial output data Dout. In particular, as shown in FIGS. 6 and 7, in the serial output section, if a wiring delay that cannot be neglected occurs in a wiring L between the clock input SC and the serial output data Dout, a serial access time is adversely prolonged. Reference symbol Bi denotes an SC clock input buffer; Bo, a data output buffer; and SR4, a last shift register.
A serial access time required for the image memory is 10 ns to, 20 ns. This serial access time must be even shorter for, e.g., a high-quality television receiver with a large screen size which uses an image memory. As memory capacity increases, an increased wiring delay further increases an access time.
On the other hand, an image memory has a larger capacity and a larger number of high-speed serial ports, e.g., a television receiver which has high quality and a larger screen size and which uses an image memory. In the image memory shown in FIG. 1, the serial input and output sections may be preferably arranged adjacent to the memory cell array. If the serial input and output sections are arranged adjacent to the memory cell array, the layout of the peripheral sections of the memory cell array becomes difficult, and a chip size and the number of external signal pins are undesirably increased along with the development of a high-capacity and multibit image memory.
More specifically, in order to achieve a highspeed operation, the number of shift registers must be increased because of the restriction of a read/write cycle of the RAM section. The number of shift registers is increased as the number of ports is increased, and the number of bits is also increased when the RAM section has a larger capacity. Therefore, a 4-bit image memory having three independent serial I/O ports requires 24 shift registers. In this case, a large number of external signal pins are required to perform control and input/output operations of the serial section, except for the external signal pins required for the RAM section.
When a multibit, high-speed serial port is developed, an external load of the semiconductor integrated circuit becomes large. As a result, a charge/discharge current is increased, and a variation (to be referred to as output noise hereinafter) in power source or ground potential is increased. In a serial access memory, a high-impedance period of an output does not exist, and data are continuously output. Therefore, a voltage amplitude of an output and its time change dV/dt are large in comparison to those in a conventional random access memory.
Therefore, output noise is further increased, and operations of the circuits in the memory may be adversely affected.
FIG. 8 is a timing chart of an operation when the potential of the clock input SC is changed due to output noise in the circuit in the serial output section shown in FIG. 4. More specifically, when the clock input SC goes to level "H" from level "L", the output Dout is switched, and the external load is charged or discharged at this time. Therefore, the ground potential of the integrated circuit varies. Therefore, in the integrated circuit, the potential of the clock input SC seems to be changed when the output Dout is switched, as shown in FIG. 8. In addition, when the output Dout goes to level "H" from level "L", i.e., when the electric charges in the external load are discharged to the ground potential in the integrated circuit, an adverse effect due to the output noise becomes more noticeable.
The registers SR1 to SR4 hold and output data of the immediately preceding cycle when the clock SC is set at level "L". In addition, the registers SR1 to SR4 receive outputs from the selectors Y1 to Y4, through.. the input terminals thereof, output the data, that is received when the clock SC is set at level "H", and invalidate the data input to the input terminals.
At a trailing edge of the output Dout, electric charges are discharged from the external load capacitor to ground, and hence the ground potential of the semiconductor memory is temporarily increased. At this time, all the potentials in the semiconductor memory are determined with reference to the internal ground potential. Therefore, the external clock input SC seems to be "L" at this moment (shown surrounded by a broken line in FIG. 8). Therefore, the shift registers SR1 to SR4 receive new data during a period of time when input data is to be invalidated, and an output is switched. In other words, a data transfer error undesirably occurs.
FIG. 9 shows a circuit in which a noise filter NF is inserted in a supply path of the clock input SC, to suppress the above-mentioned variation in potential of the clock input SC due to output noise. An example of operation waveforms obtained when such an arrangement is employed are shown in FIG. 10. Even if the potential of the clock input SC varies due to the output noise, a potential variation in clock input SC' passed through the noise filter NF is suppressed. Therefore, a data transfer error of the shift registers SR1 to SR4 can be prevented.
Since the clock input SC' is delayed from the clock input SC by a delay time of the noise filter, timings of a data transfer operation of the shift registers SR1 to SR4 are delayed as compared with a case wherein the noise filter NF is not inserted. More specifically, in the circuit shown in FIG. 9, a serial access time (time until the output Dout is switched from a leading edge of the clock input SC) is undesirably delayed as a side effect of prevention of an operation error of the circuit due to output noise.